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Behind the research – meet Peter Gleeson, an Intel Researcher in Residence

Intel's Peter Gleeson gives a glimpse into the role of a researcher in residence

This month marks 32 years of Intel operations in Ireland. A lot has changed in those 32 years as Intel’s presence in Ireland has grown and evolved and today there are nearly 5,000 people who work for Intel in Ireland. The majority of our employees in Ireland support our manufacturing operations in Leixlip, where we manufacture 14nm products at volume and are preparing to bring Intel 4 technology online in our expanded fab development. The journey of manufacturing over the past 3 decades has helped to drive opportunities in a number of other important areas – one being that of research. We recently caught up with Peter Gleeson, an Intel Ireland employee who works as a researcher in residence. 


How long have you worked at Intel?
I have been working at Intel since 2003.

What university do you primarily work with?

I have been based in Trinity College Dublin since I started in the researcher in residence role. I also support colleagues in DCU where they require the facilities available in the CRANN institute in Trinity.

Can you tell us about what is involved in being a researcher in residence?

I work as a hands-on researcher embedded in the academic research team. The work I do has been varied as is perhaps best illustrated by examples from my work down through the years. During my time at Intel, I have seen Moore’s Law in action as we have transitioned from the 90nm technology node towards the 20A Angstrom era in a few generation’s time. All these devices are based on thermionic emission over an energy barrier with the associated 60mV / dec subthreshold swing limit. A few years ago, I was involved in a project to look at ways of improving on this by utilising a mechanical switch to overcome the subthreshold leakage. My contribution to this project involved utilising multiple nanoscale cantilevers to explore mechanical behaviour at the nanoscale.

As transistors are scaled, the interconnect wiring must also be scaled. Another interesting project involved the use of Scanning Tunnelling Microscopy to explore the behaviour of metals scaled to these demanding interconnect dimensions. The technique exploits the exponential dependence of a tunnelling current on the width of a physical gap (on the order of a nm) between a piezo mounted sharp metallic tip, and the material under investigation. The work gave us some insight in the behaviour of materials at these length scales.

It’s not all white coat and goggles research! An ongoing project involves work to improve the accuracy of Density Functional Theory (DFT) methods to simulate the electronic structure of various materials. Ultimately, this will allow my Components Research colleagues to exploit the improvement as they model materials that are of interest to Intel.

What are some of your key responsibilities?

My role is to provide hands on research support to my academic colleagues. On a current project exploring chemical infiltration into polymers for the purpose of “bottom up” self assembly based patterning, my contribution is to electrically characterise novel thin films. To do this I run a “mini fab” where I use bench top scale wet etch and plasma ash techniques to prepare the films. I then use electron beam and UV lithography to pattern contact pads which are metallised in an evaporator and then lifted off in acetone.

My role also involves scanning the research ecosystem to identify where university research might map on to the Intel roadmap. I occasionally work on early-stage projects to progress the work towards the point where a funded project is established.

A key part of the role involves mentoring PhD students, and working to support the talent pipeline. As the Intel researcher in the CRANN institute in Trinity, I use my profile to represent Intel and promote the professional careers available to graduates at Intel.

What research project(s) are you currently working on?

I am working on two projects funded by my colleagues at Components Research. The first of these is an exploration of ways to address the fact that DFT approximations can and do occasionally fail in an unpredictable manner. By tweaking the simulation, my academic colleagues are attempting to enable the DFT simulation to self-correct. If successful, the technique could be brought to bear in the simulation of materials of interest to my CR colleagues. The second project is in an area where our research team has been active for many years. The focus of the project is on novel patterning using directed self-assembly (DSA), and specifically on ways to infiltrate polymers to drive new behaviour and functionality.

In your world of work, what are you excited about for the coming years?

During my time at Intel, I have seen how innovation has driven Moore’s Law. From straining Si to enhance mobility to high K / metal gate stacks to reduce leakage, and on to our more recent architectural innovation in the FinFET and SuperFin, we have driven the industry forward. As I look ahead, I am excited by our continued commitment to innovating developments such as EUV at the Intel 4 node right down to GAA technology at the Angstrom era. Exciting times ahead!

As innovation underpins Intel’s success, it is a privilege to work as a researcher in residence, and I look forward to our onward march to the Angstrom era.


Read more – Research Manager Bernie Capraro shares an insight into Intel’s research programme in Ireland


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